Senior Hardware Design Verification Engineer, Paris

Senior Hardware Design Verification Engineer, Paris France. 

We are looking for a Verification Engineer to work on cutting-edge SoC projects, contributing to the development and verification of advanced test benches. This role involves writing and executing verification plans for highly parametrized IPs, with a focus on UVM, Python, C++, and SystemVerilog.

Key Responsibilities:

• Develop and debug advanced UVM test benches.
• Write and execute RTL verification tests for complex IPs.
• Perform performance and power-aware verification.
• Troubleshoot regressions and debug RTL designs.
• Improve verification processes, methodologies, and metrics.
• Lead verification efforts on complex SoC projects.

Experience & Qualifications:

• 7+ years of experience in verification.
• Strong knowledge of Verilog/SystemVerilog.
• Familiarity with interconnect technology, cache architecture, and AMBA protocols.
• Experience with C++, Python, or JavaScript is a plus.
• Fluent in French and English.
• Autonomous, detail-oriented, and team-driven.

Education: Master’s Degree in Engineering.