Senior Verification Engineer, Sophia-Antipolis, France

Your Role:

• Define, document, and develop RTL verification tests/coverage for highly parameterized IPs using Python and C++, compatible with major RTL simulators (e.g., Cadence, Synopsys).
• Enhance verification workflows, refine metrics, and increase automation.
• Develop and maintain verification components like BFMs or monitors for test benches.

Required Experience/Qualifications:

• Minimum of 4 years of industry experience in verification engineering.
• Proficiency in hardware RTL design and verification languages (e.g., VHDL, Verilog, SystemC, C++, Python, SystemVerilog).
• Expertise in developing and using verification methods and infrastructure (VIPs, UVMs, testbeds, EDA tools).
• Experience with formal proof verification methodology is a plus.
• Familiarity with shell scripting and interconnect technologies is advantageous.
• Understanding of hardware communication protocols (e.g., AMBA, OCP).
• Strong communication skills in French and English.
• Curious, autonomous, rigorous, and results-driven, with a commitment to quality and teamwork.

Are you ready to bring your expertise to a cutting-edge team driving the future of system-on-chip innovation? Apply today.